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march 2007 rev. 2 w7ncf-h-m1 series 1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs features ? storage capacities: ? 128mb, 256mb, 512mb,1gb, 2gb, 4gb and 8gb ? environment conditions: ? operating temperature: -40c to 85c ? storage temperature: -55c to 125c ? compactflash ? compatibility ? cfa standard 2.1 compliant ? 3.3v or 5.0v single power supply ? 50 pin connector with type-i form factor (3.3mm thickness) ? 256 bytes of attribute memory ? power consumption ? 5v operation active mode: write operation: 28 ma (typ.), 30 ma (max.) read operation: 23 ma (typ.), 30 ma (max.) sleep mode: 2.0ma (max.) ? 3.3v operation active mode: write operation: 28 ma (typ.), 30 ma (max.) read operation: 23 ma (typ.), 30 ma (max.) sleep mode: 2.0ma (max. ? rohs compliant ? interface modes ? pc card memory mode ? pc card i/o mode ? true ide mode ? less than 1 error in 10 14 bits read ? mtbf > 4,000,000 hours ? high shock & vibration tolerance ? w/e endurance: 4,000,000 write/erase cycles ? high performance ? interface transfer speed in pio mode 4 or multi word dma mode 2 cycle timing; up to 16.7 mb/second (pio mode 3 & 4 are available in ide mode only). ? typical write: 5.0 mbytes/s in ata pio mode 4 ? typical read: 7.0 mbytes/s in ata pio mode 4 ? on card ecc up to 6 bytes per 512 byte data medical series compactflash? card 4 gb 2 gb sector ? dimensions: ? type i card : 36.4mm(l) x 42.8mm(w) x 3.3mm(h) ? highly resistant to data corruption due to power loss or card removal description the w7ncf-h-m1 series compactflash? family is designed for high reliability and robust operation. this product not only offers a strictly controlled and locked bill of materials but also the robust operation which is desired in many medical applications. the product?s reliability backbone is established by using a 32 bit risc based controller along with the best slc (single level cell) nand ash memory devices. utilizing proprietary techniques, our card offers both rmware and hardware features which mitigate problems relating to power disturbances and interruptions. implemented is the industry leading ecc protection which is capable of correcting 6 bytes in every 512 byte sector. this leading ecc protection combined with patented static wear leveling technology provides the highest read/write endurance possible. compactflash? is a trademark of sandisk corporation and is licensed royalty-free to the cfa, which in turn will license it royalty-free to cfa members. cfa: compactflash ? association.
march 2007 rev. 2 w7ncf-h-m1 series 2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs environmental characterization item performance temperature cycle jedec - jesd std a104 temp condition n (-40c to 85 c) and soak mode 3; 200 cycles humidity mil-std 810f, method 507.4, paragraph 4.5.2 - 10 day test per gure 507.4-1, 10 day test vibration mil-std 810f, method 514.5, procedure 1, category 24, 1 hour per axis shock mil-std 810f, method 516.5, procedure1, non-operational, 40g, srs functional shock for ground equipment, three (3) shock per axis (positive or negative). jedec- jesd22-b, 104-a, test condition b,1500 g pulse, 0.5 msec altitude mil-std 810f, method 500.4, procedure ii, modi ed to 80,000 ft and non operation 1 hr test duration at altitude product reliability item value mtbf (@ 25c) > 4,000,000 hours data reliability < 1 non-recoverable error in 10 14 bits read endurance > 4,000,000 write/erase cycles product performance item performance (pio mode 4 true ide) read transfer rate (typical) 7mb/s write transfer rate (typical) 5mb/s burst transfer rate up to 16.7mb/s controller overhead (command to drq) 1ms typical, 5ms (max)
march 2007 rev. 2 w7ncf-h-m1 series 3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs dc electrical characteristics symbol parameter min max units notes v il input low voltage -0.3 +0.8 v v ih input high voltage 2.0 vcc+0.3 v v ol output low voltage 0.45 v at 4ma v oh output high voltage 2.4 v at 4ma i cc operating current, v cc_r=5.0v sleep mode 0.2 ma operating, 20 mhz 30 ma i cc operating current, v cc_r=3.3v sleep mode 0.2 ma operating, 20 mhz 30 ma i li input leakage current 10 a i lo output leakage current 10 a attribute memory read and write ac characteristics v cc = 5v 0.5v, 3.3 v 0.3v symbol parameter min max units t cr read cycle time 250 ns t a(a) address access time 250 ns t a(ce) card enable access time 250 ns t a(oe) output enable access time 125 ns t dis(ce) output disable time from ce 100 ns t dis(oe) output disable time from oe 100 ns t en(ce) output enable time from ce 5 ns t en(oe) output enable time from oe 5 ns t v(a) data valid time from address change 0 ns t su(a) address setup time 30 ns t h(a) address hold time 20 ns t su(ce) card enable setup time 2 ns t h(ce) card enable hold time 20 ns t cw write cycle time 250 ns t w(we) write pulse time 150 ns t su(a-weh) address setup time for we 180 ns t su(ce-weh) card enable setup time for we 180 ns t su(d-weh) data setup time for we 80 ns t h(d) data hold time 30 ns t dis(we) output disable time from we ns t en(we) output enable time from we 5 100 ns t su(oe-we) output enable setup time for we 10 ns t h(oe-we) output enable hold time from we 10 ns
march 2007 rev. 2 w7ncf-h-m1 series 4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs common memory read and write ac charateristics symbol parameter min max units t cr read cycle time 150 ns t a(a) address access time 150 ns t a(ce) card enable access time 150 ns t a(oe) output enable access time 75 ns t dis(ce) output disable time from ce 75 ns t dis(oe) output disable time from oe 75 ns t en(ce) output enable time from ce 5 ns t en(oe) output enable time from oe 5 ns t v(a) data valid time from address change 0 ns t su(a) address setup time 20 ns t h(a) address hold time 20 ns t su(ce) card enable setup time 0 ns t h(ce) card enable hold time 20 ns t cw write cycle time 150 ns t w(we) write pulse time 80 ns t su(a-weh) address setup time for we 100 ns t su(ce-weh) card enable setup time for we 100 ns t su(d-weh) data setup time for we 50 ns t h(d) data hold time 20 ns t rec(we) 20 t dis(we) output disable time from we ns t en(we) output enable time from we 5 75 ns t su(oe-we) output enable setup time for we 10 ns t h(oe-we) output enable hold time from we 10 ns
march 2007 rev. 2 w7ncf-h-m1 series 5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs i/o access read and write ac characteristic symbol parameter min max units t d(iord) data delay after iord 100 ns t h(iord) data hold following iord 0 ns t w(iord) iord pulse width 165 ns t sua(iord) address setup time for iord 70 ns t ha(iord) address hold time for iord 20 ns t suce(iord) card enable setup time for iord 5 ns t hce(iord) card enable hold time from iord 20 ns t sureg(iord) reg setup time for iord 5 ns t hreg(iord) reg hold time from iord 0 ns t d np(iord) inpack delay falling from iord 0 45 ns t drlnp(iord) inpack delay rising from iord 45 ns t d o16(iord) iois16 delay falling from address 35 ns t drlo16(iord) iois16 delay rising from address 35 ns t su(iowr) data setup time for iowr 60 ns t h(iowr) data hold time from iowr 30 ns t w(iowr) iowr pulse width 165 ns t sua(iowr) address setup time for iowr 70 ns t ha(iowr) address hold time from iowr 20 ns t suce(iowr) card enable setup time fro iowr 5 ns t hce(iowr) card enable hold time from iowr 20 ns t sureg(iowr) reg setup time for iowr 5 ns t hreg(iowr) reg hold tme from iowr 0 ns true-ide mode i/o access read and write ac characteristics symbol parameter min max units t cr cycle time 120 ns t sua address setup time for iord/iowr 25 ns t ha address hold time from iord/iowr 10 ns t w iord/iorw pulse width 70 ns t rec iord/iorw recovery time 25 ns t sud(iord) data setup time for iord 20 ns t hd(iord) data hold time for iord 5 ns t dis(iord) output disable time from iord 30 ns t sud(iowr) data setup time for iowr 20 ns t hd(iowr) data hold following iowr 10 ns
march 2007 rev. 2 w7ncf-h-m1 series 6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pin assignments & pin type pc card memory mode pin number signal name pin type in, out type 1 gnd ground 2 d03 i/o i1z, oz3 3 d04 i/o i1z, oz3 4 d05 i/o i1z, oz3 5 d06 i/o i1z, oz3 6 d07 i/o i1z, oz3 7 -ce1 i i3u 8 a10 i iz1 9 -oe i iu3 10 a09 i i1z 11 a08 i i1z 12 a07 i i1z 13 v cc power 14 a06 i i1z 15 a05 i i1z 16 a04 i i1z 17 a03 i i1z 18 a02 i i1z 19 a01 i i1z 20 a00 i i1z 21 d00 i/o i1z, oz3 22 d01 i/o i1z, oz3 23 d02 i/o i1z, oz3 24 wp o ot3 25 -cd2 o ground 26 -cd1 o ground 27 d11 1 i/o i1z, oz3 28 d12 1 i/o i1z, oz3 29 d13 1 i/o i1z, oz3 30 d14 1 i/o i1z, oz3 31 d15 1 i/o i1z, oz3 32 -ce2 1 i i3u 33 -vs1 o ground 34 -iord i i3u 35 -iowr i i3u 36 -we i i3u 37 rdy o ot1 38 v cc power 39 -csel 4 i i2z 40 -vs2 o open 41 reset i i2z 42 -wait o ot1 43 -inpack o ot1 44 -reg i i3u 45 bvd 2 o ot1 46 bvd 1 o ot1 47 do8 1 i/o i1z, oz3 48 do9 1 i/o i1z, oz3 49 d10 1 i/o i1z, oz3 50 gnd ground pc card i/o mode pin number signal name pin type in, out type 1 gnd ground 2 d03 i/o i1z, oz3 3 d04 i/o i1z, oz3 4 d05 i/o i1z, oz3 5 d06 i/o i1z, oz3 6 d07 i/o i1z, oz3 7 -ce1 i i3u 8 a10 i iz1 9 -oe i iu3 10 a09 i i1z 11 a08 i i1z 12 a07 i i1z 13 v cc power 14 a06 i i1z 15 a05 i i1z 16 a04 i i1z 17 a03 i i1z 18 a02 i i1z 19 a01 i i1z 20 a00 i i1z 21 d00 i/o i1z, oz3 22 d01 i/o i1z, oz3 23 d02 i/o i1z, oz3 24 -iois16 o ot3 25 -cd2 o ground 26 -cd1 o ground 27 d11 1 i/o i1z, oz3 28 d12 1 i/o i1z, oz3 29 d13 1 i/o i1z, oz3 30 d14 1 i/o i1z, oz3 31 d15 1 i/o i1z, oz3 32 -ce2 1 i i3u 33 -vs1 o ground 34 -iord i i3u 35 -iowr i i3u 36 -we i i3u 37 ireq o ot1 38 v cc power 39 -csel 4 i i2z 40 -vs2 o open 41 reset i i2z 42 -wait o ot1 43 -inpack o ot1 44 -reg i i3u 45 -spkr i/o ot1 46 -stschg i/o ot1 47 do8 1 i/o i1z, oz3 48 do9 1 i/o i1z, oz3 49 d10 1 i/o i1z, oz3 50 gnd ground true ide mode pin number signal name pin type in, out type 1 gnd ground 2 d03 i/o i1z, oz3 3 d04 i/o i1z, oz3 4 d05 i/o i1z, oz3 5 d06 i/o i1z, oz3 6 d07 i/o i1z, oz3 7 -cs0 i i3u 8 a10 2 i iz1 9 -ata sel i iu3 10 a09 2 i i1z 11 a08 2 i i1z 12 a07 2 i i1z 13 v cc power 14 a06 2 i i1z 15 a05 2 i i1z 16 a04 2 i i1z 17 a03 2 i i1z 18 a02 i i1z 19 a01 i i1z 20 a00 i i1z 21 d00 i/o i1z, oz3 22 d01 i/o i1z, oz3 23 d02 i/o i1z, oz3 24 -iois16 o on3 25 -cd2 o ground 26 -cd1 o ground 27 d11 1 i/o i1z, oz3 28 d12 1 i/o i1z, oz3 29 d13 1 i/o i1z, oz3 30 d14 1 i/o i1z, oz3 31 d15 1 i/o i1z, oz3 32 -cs1 1 i i3z 33 -vs1 o ground 34 -iord i i3z 35 -iowr i i3z 36 -we 3 i i3u 37 ireq o oz1 38 v cc power 39 -csel i i2u 40 -vs2 o open 41 reset i i2z 42 -iordy o on1 43 dmarq o oz1 44 -dmack 5 i i3u 45 -dasp i/o i1u, on1 46 pdiag i/o i1u, on1 47 do8 1 i/o i1z, oz3 48 do9 1 i/o i1z, oz3 49 d10 1 i/o i1z, oz3 50 gnd ground note: 1 these signals are required only for 16-bit access and are not required when installed in 8-bit systems. devices should allow for 3-state signals not to consume current. 2 : should be grounded by the host system. 3 : should be tied to v cc by the host system. 4 : the -csel signal is ignored by the card in pc card moudes. however, because it is not pulled up on the card in thses modes, it should not be left oating by the host in pc card modes. in these modes, the pin should be connected by th host to pc card a25 or grounded by the host. 5 : if dma operations are not used, the signal should be held high or tied to v cc by the host. for proper operation in older hosts: while dma operations are not active, the card shall ignore the signal, including a oating condition.
march 2007 rev. 2 w7ncf-h-m1 series 7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs signal description signal name dir. pin description a10-a0 (pc card memory mode) i 8, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20 these address lines along with the -reg signal are used to select the following: the i/o port address registers within the compactflash? storage card or cf+ card, the memory mapped port address registers within the compactflash? storage card or cf+ card, a byte in the card's information structure and its con guration control and status registers. a10-a0 (pc card i/o mode) this signal is the same as the pc card memory mode signal. a2 - a0 (true ide mode) 18, 19, 20 in true ide mode, only a[2:0] are used to select the one of eight registers in the task file, the remaining address lines should be grounded by the host. bvd1 (pc card memory mode) i/o 46 this signal is asserted high, as bvd1 is not supported. -stschg (pc card i/o mde) status changed this signal is asserted low to alert the host to changes in the ready and write protect states , while the i/o interface is con gured. its use is controlled by the card con g and status register. -pdiag (true ide mode) in the true ide mode, this input / output is the pass diagnostic signal in the master / slave handshake protocol. bvd2 (pc card memory mode) i/o 45 this signal is asserted high, as bvd2 is not supported. -spkr (pc card i/o mode) this line is the binary audio out put from the card. if the card does not support the binary audio function, this line should be held negated. -dasp (true ide mode) in the true ide mode, this input/output is the disk active/slave present signal in the master/ slave handshake protocol. -cd1, -cd2 (pc card memory mode) o 26, 25 these card detect pins are connected to ground on the compactflash? storage card or cf+ card. they are used by the host to determine that the compactflash? storage card or cf+ card is fully inserted into its socket. -cd1, cd2 (pc card i/o mode) this signal is the same for all modes. -cd1, cd2 (true ide mode) this signal is the same for all modes. -ce1, -ce2 (pc card memory mode) card enable i 7, 32 these input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -ce2 always accesses the odd byte of the word. -ce1 accesses the even byte or the odd byte of the word depending on a0 and -ce2. a multiplexing scheme based on a0, -ce1, -ce2 allows 8 bit hosts to access all data on d0-d7. -ce1, -ce2 (pc card i/o mode) card enable this signal is the same as the pc card memory mode signal. -cs0, cs1 (true ide mode) in the true ide mode, -cs0 is the chip select for the task le registers while -cs1 is used to select the alternate status register and the device control register. while ?dmack is asserted, -cs0 and ?cs1 shall be held negated and the width of the transfers shall be 16 bits. -csel (pc card memory mode) i39 this signal is not used for this mode, but should be connected by the host to pc card a25 or grounded by the host. -csel (pc card i/o mode) this signal is not used for this mode, but should be connected by the host to pc card a25 or grounded by the host. -csel (true ide mode) this internally pulled up signal is used to con gure this device as a master or a slave when con gured in the true ide mode. when this pin is grounded, this device is con gured as a master. when the pin is open, this device is con gured as a slave.
march 2007 rev. 2 w7ncf-h-m1 series 8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs signal name dir. pin description d15 - d00 (pc card memory mode) i/o 31, 30, 29, 28, 27, 49, 48, 47, 6, 5, 4, 3, 2, 23, 22, 21 these lines carry the data, commands and status information between the host and the controller . d00 is the lsb of the even byte of the word. d08 is the lsb of the odd byte of the word. d15 - d00 (pc card i/o mode) this signal is the same as the pc card memory mode signal. d15 - d00 (true ide mode) in true ide mode, all task file operations occur in byte mode on the low order bus d[7:0] while all data transfers are 16 bit using d[15:0]. gnd (pc card memory mode) - 1, 50 ground gnd (pc card i/o mode) this signal is the same for all modes. gnd (true ide mode) this signal is the same for all modes. -inpack (pc card memory mode) o43 this signal is the same for all modes. -inpack (pc card i/o mode) input acknowledge the input acknowledge signal is asserted by the compactflash? storage card or cf+ card when the card is selected and responding to an i/o read cycle at the address that is on the address bus. this signal is used by the host to control the enable of any input data buffers between the compactflash? storage card or cf+ card and the cpu. dmarq (true ide mode) this signal is a dma request that is used for dma data transfers between host and device. it shall be asserted by the device when it is ready to transfer data to or from the host. for multiword dma transfers, the direction of data transfer is controlled by dior- and diow-. this signal is used in a handshake manner with dmack-, i.e., the device shall wait until the host asserts dmack- before negating dmarq, and re asserting dmarq if there is more data to transfer. while a dma operation is in progress, -cs0 and ?cs1 shall be held negated and the width of the transfers shall be 16 bits. if there is no hardware support for dma mode in the host, this output signal is not used and should not be connected at the host. in this case, the bios must report that dma mode is not supported by the host so that device drivers will not attempt dma mode. a host that does not support dma mode and implements both pcmcia and true-ide modes of operation need not alter the pcmcia mode connections while in true-ide mode as long as this does not prevent proper operation in any mode. -iord (pc card memory mode) i34 this signal is not used in this mode. -iord (pc card i/o mode) this is an i/o read strobe generated by the host. this signal gates i/o data onto the bus from the compactflash? storage card or cf+ card when the card is con gured to use the i/o interface. -iord (tru ide mode) in true ide mode, this signal has the same function as in pc card i/o mode. signal description (con'd)
march 2007 rev. 2 w7ncf-h-m1 series 9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs signal name dir. pin description -iowr (pc card memory mode) i35 this signal is not used in this mode. -iowr (pc card i/o mode) the i/o write strobe pulse is used to clock i/o data on the card data bus into the compactflash? storage card or cf+ card controller registers when the compactflash? storage card or cf+ card is con gured to use the i/o interface. the clocking shall occur on the negative to positive edge of the signal (trailing edge). -iowr (true ide mode) in true ide mode, this signal has the same function as in pc card i/o mode. -oe (pc card memory mode) i9 this is an output enable strobe generated by the host interface. it is used to read data from the compactflash? storage card or cf+ card in memory mode and to read the cis and con guration registers. -oe (pc card i/o mode) in pc card i/o mode, this signal is used to read the cis and con guration registers. -ata sel (true ide mode) to enable true ide mode this input should be grounded by the host. ready (pc card memory mode) o37 in memory mode, this signal is set high when the compactflash? storage card or cf+ card is ready to accept a new data transfer operation and is held low when the card is busy. at power up and at reset, the ready signal is held low (busy) until the compactflash? storage card or cf+ card has completed its power up or reset function. no access of any type should be made to the compactflash? storage card or cf+ card during this time. note, however, that when a card is powered up and used with reset continuously disconnected or asserted, the reset function of the reset pin is disabled. consequently, the continuous assertion of reset from the application of power shall not cause the ready signal to remain continuously in the busy state. -ireq (pc card i/o mode) i/o operation ? after the compactflash? storage card or cf+ card has been con gured for i/o operation, this signal is used as -interrupt request. this line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. intrq in true ide mode signal is the active high interrupt request to the host. signal name dir. pin description -reg (pc card memory mode) attribute memory select i44 this signal is used during memory cycles to distinguish between common memory and register (attribute) memory accesses. high for common memory, low for attribute memory. -reg (pc card i/o mode) the signal shall also be active (low) during i/o cycles when the i/o address is on the bus. -dmack (true ide mode) this is a dma acknowledge signal that is asserted by the host in response to dmarq to initiate dma transfers. while dma operations are not active, the card shall ignore the -dmack signal, including a oating condition. if dma operation is not supported by a true ide mode only host, this signal should be driven high or connected to vcc by the host. a host that does not support dma mode and implements both pcmcia and true-ide modes of operation need not alter the pcmcia mode connections while in true-ide mode as long as this does not prevent proper operation all modes. signal description (con'd)
march 2007 rev. 2 w7ncf-h-m1 series 10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs signal name dir. pin description reset (pc card memory mode) i41 the compactflash? storage card or cf+ card is reset when the reset pin is high with the following important exception: the host may leave the reset pin open or keep it continually high from the application of power without causing a continuous reset of the card. under either of these conditions, the card shall emerge from power-up having completed an initial reset. the compactflash? storage card or cf+ card is also reset when the soft reset bit in the card con guration option register is set. reset (card i/o mode) this signal is the same as the pc card memory mode signal. -reset (true ide mode) in the true ide mode, this input pin is the active low hardware reset from the host. vcc (pc card memory mode) - 13, 38 +5 v, +3.3 v power. vcc (pc card i/o mode) this signal is the same for all modes. vcc (true ide mode) this signal is the same for all modes. -vs1 -vs2 (pc card memory mode) o 33, 40 voltage sense signals. -vs1 is grounded on the card and sensed by the host so that the compactflash? storage card or cf+ card cis can be read at 3.3 volts and -vs2 is reserved by pcmcia for a secondary voltage and is not connected on the card. -vs1 -vs2 (pc card i/o mode) this signal is the same for all modes. -vs1 -vs2 (true ide mode) this signal is the same for all modes. -wait (pc card memory mode) o42 the -wait signal is driven low by the compactflash? storage card or cf+ card to signal the host to delay completion of a memory or i/o cycle that is in progress. -wait (pc card i/o mode) this signal is the same as the pc card memory mode signal. iordy (true ide mode) in true ide mode, this output signal may be used as iordy. -we (pc card memory moce) i36 this is a signal driven by the host and used for strobing memory write data to the registers of the compactflash? storage card or cf+ card when the card is con gured in the memory interface mode. it is also used for writing the con guration registers. -we (pc card i/o mode) in pc card i/o mode, this signal is used for writing the con guration registers. -we (true ide mode) in true ide mode, this input signal is not used and should be connected to vcc by the host. wp (pc card memory mode) o24 memory mode ? the compactflash? storage card or cf+ card does not have a write protect switch. this signal is held low after the completion of the reset initialization sequence. -iois16 (pc card i/o model) i/o operation ? when the compactflash? storage card or cf+ card is con gured for i/o operation pin 24 is used for the -i/o selected is 16 bit port (-iois16) function. a low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. -iocs16 (true ide mode) in true ide mode this output signal is asserted low when this device is expecting a word data transfer cycle. signal description (con'd)
march 2007 rev. 2 w7ncf-h-m1 series 11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs all dimensions are in millimeters and (inches) 4xr 0.5mm .1 (4xr.020 in .004) 41.66mm 1.65mm (.130 in.) .13(1.640 in . 005) 42.80mm .10(1.685 in .004) 0.63mm .07(.025 in .003) 26 50 125 .99mm .05 (.039 in .002) .01mm .07(.039 in .003) 3.30mm .10 (.130 in .004) 1.60mm .05 (.063 in .002) 0.76mm .07(0.30 in .003) m m 0 0 . 3 x 2 7 0 . n i 8 1 1 . x 2 ( . ) 3 0 0 m m 0 4 . 6 3 n i 3 3 4 . 1 ( 5 1 . . ) 6 0 0 m m 8 7 . 5 2 x 2 5 1 0 . 1 x 2 ( 7 0 ..) 3 0 0 m m 0 0 . 2 1 x 20 1 . n i 2 7 4 x 2 (. ) 4 0 0 2.15mm 2.44mm .07 (.096 in. .003) optional configuration (see note.) 1.01mm .07 (0.040 in. .003) 1.01mm .07 (0.040 in. .003) .07 (.085 in x .003) note: the optional notched configuration was shown in the cf specification rev. 1.0 in specification rev. 1.2, the notch was removed for ease of tooling. this optional configuration can be used but it is not recommended. package dimensions
march 2007 rev. 2 w7ncf-h-m1 series 12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs part numbering guide w 7n cf xxx h x 0 x x x x x m1 x wedc: flash card, slc - nand: compactflash?: memory capacity: 128 = 128m byte 256 = 256m byte 512 = 512m byte 01g = 1g byte 02g = 2g byte 04g = 4g byte 08g = 8g byte controller manufacturer h = h-series controller/firmware revision number: 1, 2, 3... labels or custom labeling: 0 = labels front and back 1 = label on back only temperature: c = commercial (0c - 70c) i = industrial (-40c - +85c) memory mfg.: s = samsung memory vendor revsison: blank = initial release a = susequent release etc. memory device information: option: market series: m1 = medical series 1 g = for rohs: 2 = 512mbit single die package 7 = 8gb dual die package 3 = 1gb single die package 8 = 8gb single die package 4 = 2gb single die package 9 = 16gb quad die package 5 = 4gb dual die package a = 16gb dual die package 6 = 4gb single die package b = 16gb single die package * for help selecting the proper and most current part number for your application please contact your local sales representati ve. b = standard cf card con guration a = standard cf with conformal coating c = standard card with dma disabled d = standard card with dma disabled and conformal coating e = fixed disk option (for compatibility with some embedded software) f = fixed disk with conformal coating h = fixed with dma disable j = fixed disk with dma disable and conformal coating
march 2007 rev. 2 w7ncf-h-m1 series 13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs document title 128mb to 8gb medical series compactflash? revision history rev # history release date status rev 0 initial release february 2007 concept rev 1 1.0 reviewed by enginerieng 1.1 moved from concept to advanced march 2007 advanced rev 2 2.0 added 1gb density to storage capacites march 2007 advanced

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